O Introduction
With the rapid development of USB technology, USB mobile storage devices are becoming more and more widely used. Currently, USB interfaces are provided on some instruments with data acquisition and analysis functions. Among many USB mobile storage device interface chips, CH375 is a domestic chip with extremely high cost performance. Here are some practical experiences in applying the chip in the battery activation detection device for the reader's reference.
1 CH375 function and features
1.1 Chip Overview
CH375 is a USB bus universal interface circuit that supports HOST host mode and SLAVE device mode. At the local end, the CH375 has an 8-bit data bus and read, write, chip select control lines and interrupt outputs, which can be easily hooked up to the system bus of the microcontroller/DSP/MCU/MPU controller. In the USB host mode, serial communication mode is provided, which is connected to the MCU/DSP/MCU/MPU through serial input, serial output and interrupt output. The external MCU/DSP/MCU/MPU can communicate with the USB device according to the corresponding USB protocol through the CH375, which makes the design and development of the USB work simple for the designer. The application block diagram is shown in Figure 1.
1.2 Internal structure
The CH375 integrates a PLL multiplier, a master-slave USB interface SIE, a data buffer, a passive parallel interface, an asynchronous serial interface, a command interpreter, a protocol processor for controlling transmission, and a general firmware program.
The CH375 chip has seven physical endpoints inside. Endpoint O is the default endpoint and supports uploading and downloading. The upload and download buffers are each 8 B. Endpoint 1 includes the upload endpoint and the downstream endpoint. The upload and downlink buffers are each 8 B. The endpoint number of the upload endpoint is 81H, the endpoint number of the downstream endpoint is 01H; endpoint 2 includes the upload endpoint and the downstream endpoint, the upload and downlink buffers are each 64 B, the endpoint number of the upload endpoint is 82H, and the endpoint number of the downstream endpoint is 02H. The host endpoint includes an output endpoint and an input endpoint. The output and input buffers are each 64 B. The host endpoint uses the same set of buffers as endpoint 2. The output buffer of the host endpoint is the upload buffer of endpoint 2, and the input buffer of the host endpoint. It is the downstream buffer of endpoint 2. Among them, endpoint 0, endpoint 1, and endpoint 2 of CH375 are only used in the USB device mode, and only the host endpoint is needed in the USB host mode. The CH375A internal interrupt logic diagram is shown in Figure 2.
1.3 chip characteristics
(1) Low-speed and full-speed USB-HOST host interface, support LISB 2.0, only one crystal oscillator and two capacitors for peripheral components; (2) Low-speed and full-speed USB device interface, support dynamic switching host and device mode;
(3) The host endpoint input and output buffers each have 64 B, supporting commonly used 12 Mb/s full-speed USB devices and 1.5 Mb/s low-speed devices;
(4) Support control transmission, bulk transmission, and interrupt transmission of USB devices;
(5) Automatically detect the connection and disconnection of the USB device, and provide event notification for device connection and disconnection;
(6) A protocol processor with built-in control transmission to simplify common control transmission;
(7) Built-in firmware to handle the dedicated communication protocol of the mass storage device;
(8) The parallel interface includes an 8-bit data bus, 4-wire control: read strobe, write strobe, chip select input, and interrupt output;
(9) The serial interface includes serial input, serial output and interrupt output, and supports dynamic adjustment of communication baud rate;
(10) Supports 5 V supply voltage and 3.3 V supply voltage to support low power mode.
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