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In the past decade, RF communication circuit design has made great progress. These advances are due to the new RF architecture and the architecture we once thought was impossible due to low integration, high power consumption and poor process technology. In addition, the emergence of high-performance and high-density sub-micron CMOS technology has brought digital technology into the RF field, dramatically changing the way RF communication circuits are designed. Designers have used these technologies for many wireless communication standards, such as global positioning systems (GPS), wireless networks, and mobile phones, while developing robust and highly integrated chipset solutions to improve overall system performance and reliability. Integrating external components with RF circuitry and digital baseband offers many benefits, including reduced component bills (BOM), reduced board area, simplified board level application design, and improved manufacturability.Integrating all of the system into the chip reduces the number of external components required for testing, which in turn increases the manufacturability of the product. Many modern communication applications can see examples of functional integration, but FM radio broadcast standards have not had much technological advances until recently. Even in today's digital age, many portable FM radios still require more than 15 external components. Radio manufacturers are still designing the basis for early analog technology, which mostly uses expensive and low-integration bipolar or Bi-CMOS processes.
Despite the continued growth of the FM tuner-related product market, there has been little change in its radio architecture. The emergence of a fully integrated 100% CMOS digital low-IF architecture is the first major advancement in the FM tuner radio architecture over the past decade. Prior to this, designers have used several RF architectures for FM tuners, each with its own advantages and disadvantages. For the sake of discussion, we will analyze the traditional FM transmitter and FM receiver architecture to facilitate the common architecture of the demodulation frequency system. We will also introduce the various evolutions of the FM tuner, which will eventually bring a new digital low-IF architecture to the FM receiver. In addition, we will explain how this architecture enables comprehensive and efficient integration, so that the entire FM tuner requires only one external bypass capacitor.
Figure 1: (a) FM transmitter and (b) FM receiver block diagram
Figure 1 shows a conventional FM transmitter and receiver. The FM transmitter first passes the audio signals of the left and right channels through a pre-emphasis filter, and then combines the signals with RDS (Radio Data System) data to generate a composite information signal m(t). The transmitter then modulates the information signal frequency and sends the result to the RF transmitter, which upconverts the signal to the radio frequency and produces an output signal xFM(t). Designers can use the Voltage Controlled Oscillator (VCO) to implement the FM modulator and RF transmitter functions. In theory, this direct modulation modulation method should work properly, but the designer actually uses a phase-locked loop (PLL) to stabilize the carrier frequency to avoid frequency drift while using the power amplifier to drive the antenna.
The FM receiver uses an RF receiver to reduce the RF signal xFM(t) to baseband. In an ideal situation, the FM demodulator can retrieve the original information by performing a modulation program in the reverse direction. The receiver then sends the information signal m(t) to the MPX demodulator to separate the audio from the RDS data, and then the left and right channel audio is passed through a de-emphasis circuit to eliminate the linear distortion introduced by the pre-emphasis filter. The series connection of the pre-emphasis and de-emphasis filters does not affect the left and right channel audio, but can greatly attenuate high frequency noise and interference, and theoretically increase the signal clutter ratio (SNR) by about 13 dB [1, 2].
FM tuner performance is primarily determined by the RF receiver and the FM demodulator. The most basic FM demodulator architecture is a frequency discriminator consisting of a time domain differentiator and an envelope detector. With such a demodulator, the differentiator converts the frequency modulated signal using the phase storage information into an amplitude modulated signal that uses the amplitude to store the information, and then the envelope detector retrieves the information from the amplitude. The amplitude variation of the FM carrier may destroy the demodulated output of the discriminator, so the first limiter is usually added to the front of the discriminator to remove the amplitude variation of the carrier. Other commonly used FM discriminators include the Foster-Seeley discriminator and the proportional detector [1, 2]. Manufacturers used to use FM discriminators with discrete components to design FM demodulators such as transformers, transistors, diodes, resistors and capacitors; today, most designs have adopted IC solutions.
Figure 2: Typical phase-locked loop block diagram and its linear model
The phase-locked loop is a popular FM modulation architecture. Figure 2 is a typical phase-locked loop block diagram and its linear model. Where PD stands for Phase Detector, KPD is phase detector gain, HLF(s) is the loop filter transfer function, and KVCO/s is the voltage controlled oscillator transfer function. The phase-locked loop is a negative feedback system that locks the phase of the feedback signal xVCO(t) based on the input signal xFM(t). The FM signal xFM(t) can be expressed as the following equation:
Where Ac is the carrier amplitude, fc is the carrier frequency, KVCO is the voltage/frequency conversion constant, and m(t) is the information or information signal. After the loop is locked, the phase error f e will remain unchanged. The feedback signal xVCO(t) can be expressed as the following equation:
It is constant when the loop is locked, so the control voltage sent to the voltage controlled oscillator will be equal to m(t). The negative feedback action of the phase-locked loop forces the voltage-controlled oscillator frequency to be equal to the input signal frequency; to do this, it adjusts the control voltage of the voltage-controlled oscillator to keep the phase error constant. If we remove the information signal from xFM(t), the voltage controlled oscillator frequency will lock the carrier center frequency fc and oscillate with it. After m(t) occurs, xFM(t) will deviate from the center frequency; if the loop is locked, the phase-locked loop will adjust the control voltage of the voltage-controlled oscillator to track the frequency offset of xFM(t). Since the output frequency of the voltage controlled oscillator is proportional to the control voltage (
Engineers often use phase-locked loops as FM demodulator because they allow the FM threshold to be lower than the demodulator using the discriminator [1, 4]. The phase-locked loop, frequency-locked loop (FLL), and frequency demodulator with feedback (FMFB) are closely related, and they all extend the critical value of the FM demodulator [4]. Although there are other FM demodulator architectures, designers typically use analog and digital techniques to implement these demodulators in the IC.
Figure 3: Simplified block diagram of the FM tuner RF front end
The FM tuner's radio environment consists of its target signal band, which is 88-108 MHz in the US and Europe, and 76-90 MHz in Japan. In addition, it includes all other signals within the tuner bandwidth. Figure 3 is a simplified block diagram of the FM tuner RF front end. The RF Bandpass Filter (BPF) does not attenuate the channel at the edge of the band, so it is usually designed to be slightly larger than the entire FM band. High-performance FM tuners use tight-bandwidth RF tracking filters to attenuate out-of-band and in-band interference caused by very strong FM channels. RF tracking filters require variable bandpass filters and control mechanisms to change the center frequency of the filter, so most low-cost FM receivers do not use this filter, which causes noise in the processing band and out-of-band signals. It has become one of the key requirements of RF receivers; other requirements include channel selection and small signal amplification, but this does not cause the signal clutter ratio of the information signal to drop too much.
Superheterodyne receiver
Figure 4: FM superheterodyne receiver
Until the late 1990s, almost all commercial FM broadcast receiver designs used some form of superheterodyne receiver. Figure 4 is a block diagram of a superheterodyne receiver. The superheterodyne receiver first converts the FM signal into one or more intermediate frequencies before performing FM demodulation. This block diagram is a dual IF superheterodyne receiver. The RF bandpass filter is a preselected filter that allows the FM band to pass but attenuates out-of-band interference. Designers add a low-noise amplifier (LNA) behind the RF bandpass filter, which uses the gain to attenuate the noise from subsequent stages of the circuit, improving receiver sensitivity. The mixer will downconvert the signal to a position higher than the local oscillator frequency and less than the IF frequency, so the receiver needs an image-reject BPF to select the target signal and suppress the image. signal. The mid-band pass filters IF1 BPF and IF2 BPF are fixed frequency filters that provide channel selection. The limiter removes the amplitude variation of the down-converted signal before sending it to the FM demodulator. The IF frequency of the receiver is usually lower than the RF frequency, allowing designers to easily implement less power-consuming gain and filtering.
The superheterodyne architecture spreads its gain and filtering functions to different frequency ranges, so high noise filters are not required to provide good noise and interference performance. However, this architecture requires many external components, including RF, mirror and mid-band pass filters, as well as phase-locked loop voltage-controlled oscillators and loop filters, which makes it quite large and expensive [3, 5].
Analog low IF receiver
Figure 5: Analog Low IF Receiver
The analog low-IF architecture is much like a super-heterodyne architecture with a first-level IF circuit. The main difference is that its RF phase-locked loop and mixer are designed with quadrature signals, so the built-in image cancellation function can be provided. The image frequency is twice the distance from the target signal, so if the IF signal frequency is too low, the image signal will be closer to the target signal, which will force the design to use a high-Q image suppression filter with steep edges. However, if a quadrature mixer is used, the designer can use the image cancellation technique to attenuate the image signal [3, 5, 6], even if the IF frequency is low, it will not affect. After the image removal is complete, the channel selection is then provided by the mid-band pass filter. Similarly, performing amplification (limited) and channel selection at low IF positions is easier than at high IF or RF. The main advantage of the analog low-IF receiver is that it reduces the external components required; in fact, if engineers can integrate the RF and mid-band pass filters and the RF phase-locked loop into the chip, then it does not need any External components. The biggest drawback of analog low-IF receivers is that their performance is related to analog components, which are subject to process, voltage, and temperature variations. These variations typically limit the image cancellation capability to around 25-30 dB, so the image signal may become very large with different IF choices. An oversized image signal can interfere with the target signal, and we can hear the interference at the audio output of the FM tuner at two different local oscillator frequencies. In addition, the edge-shaked IF channel filter requires a large capacitance and a large chip area. Pure analog designs typically only provide approximately 35-40 dB of adjacent channel selectivity, which makes interference performance poor. At this time, as long as a large interference signal enters the FM demodulator, the system may be overloaded or generate intermodulation distortion.
Digital low IF receiver
Figure 6: Block diagram of digital low IF receiver
Figure 6 is a block diagram of a digital low intermediate frequency receiver. The digital low-IF architecture is a mixed-signal architecture that uses an analog-to-digital converter (ADC) to convert in-phase (I) and quadrature-phase (Q) IF signals into digital IF signals, followed by digital quadrature mixing. The device downconverts the analog to digital converter output to baseband. This architecture has the integration benefits of an analog low-IF architecture and the repeatability and reliability of digital circuit implementation. Engineers can take advantage of the combination of analog and digital circuitry to provide superior image rejection because digital circuits are perfectly matched and calibrated to eliminate the shackles of analog components. Another advantage is that the IF low-pass filter does not need to provide full channel filtering. In many cases, it only needs to provide the filtering capability required for the attenuation of the alternate channel interferer and the anti-aliasing filtering required by the analog-to-digital converter ( Anti-aliasing filtering). Engineers have implemented channel filtering in the digital domain to provide steep filter drop and attenuation, and to minimize chip area and take advantage of high-density sub-micron CMOS. The biggest disadvantage of the digital low-IF architecture is that it requires a high-performance analog-to-digital converter [5]. The actual requirements depend on the intermediate frequency, the amount of interference filtering in front of the converter, and the dynamic range requirements of the input signal. This architecture has been successfully used in GSM/GPRS mobile phone receivers via the Silicon Laboratories Aero® receiver.
Practical Example – The Si4700 FM Tuner Si4700 is the industry's first radio tuner component that utilizes digital low-IF architecture and full CMOS process technology, making this fully functional integrated solution requiring only an external power supply bypass capacitor and less than 20 square millimeters of board area. Figure 7 is a block diagram of the Si4700/01 FM tuner that uses Silicon Laboratories' proven Aero digital low-IF receiver architecture and synthesizer technology to provide superior RF performance and interference rejection. The digital low-IF architecture saves external components and does not have to be factory-tuned to simulate process variations. This mixed-signal architecture allows the DSP to perform channel selection, FM demodulation, and stereo audio processing, providing greater power than traditional analog architectures.
Figure 7: Block diagram of the Si4700/01 digital low-IF FM tuner
The Si4700 FM tuner achieves a sensitivity level of 2.5μV without any external matching circuitry. It also has outstanding overload immunity, including 108dBμV IP3 and 50dB and 70dB adjacent channel selectivity and substation selectivity. The Si4700 utilizes DSP to provide the best sound quality for a variety of signal reception conditions. This high-level integration, performance and interference suppression capabilities are all derived from the digital low-IF architecture and channel selection and FM demodulation using digital technology. In addition to simplifying design and reducing development time, the digital low-IF architecture saves quality and improves manufacturability by eliminating the need for external components with high integration.
Conclusion With the FM tuner using a digital low-IF receiver architecture, a new era of FM tuner is also officially launched. The digital architecture allows FM receivers to be integrated into a single chip via CMOS technology, revolutionizing FM tuner design. The Silicon Laboratories Si4700 FM tuner not only demonstrates that this level of integration is achievable, but also provides excellent sensitivity and immunity to interference. Advances in CMOS technology will bring many benefits to digital low-IF FM tuners because all FM signal processing functions can be implemented in the digital domain. The single-chip FM tuner simplifies the design process and allows almost all portable consumer electronics devices to be easily imported into FM tuner. A fully functional system single chip also minimizes the use of external components. In addition, designers can test complete systems in the IC manufacturer's test lab to ensure that they function properly, which helps improve the quality and manufacturability of the final product. Consumer demand will eventually force portable electronics to use FM tuners, and new digital low-IF FM tuners will continue to simplify design and improve manufacturability.
Reference data
[1] S. Haykin, Communication Systems, 3rd Edition, Wiley, 1994
[2] R. E. Ziemer, W. H. Tranter, Principles of Communications, Systems, Modulation,
And Noise, Fourth Edition, Wiley, 1995
[3] B. Razavi, RF Microelectronics, Prentice Hall, 1998
[4] W. Mohr, “Rapid Approximative Calculation and Optimization of PLL-FM-Demodulator Thresholdâ€, Proc. of the IEEE Int. Symposium on Circuits and Systems, June 7-9, 1988, Helsinki Finland, pgs. 595 – 598 .
[5] T. Tuttle, Introduction to Wireless Receiver Design, ISSCC 2002 Tutorial, Feb 2002
[6] A. Abidi, “RF CMOS Comes of Ageâ€, IEEE Journal of Solid-State Circuits, vol. 39, no. 4, Apr 2004, pgs. 549 – 561
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