National Semiconductor Corporation announces a new three-speed (3G/HD/SD) audio/video clock generator for professional applications and broadcast video equipment that eliminates the need for external applications when applying such video equipment The clock is adjusted. This LMH1983 clock generator chip provides the necessary video and audio reference clocks for many different applications. In addition, the highly integrated chip's output jitter is the industry's lowest at 40ps (peak-to-peak), so the Society of Motion Picture and Television Engineers (SMPTE) standards can be achieved in applications using the FPGA serializer/deserializer.
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The LMH1983 chip replaces three external phase-locked loops (PLLs), voltage-controlled crystal oscillators (VCXOs), and loop filters. Streamline system design, save on material costs and shrink board. The LMH1983 chip is characterized by the ability to generate four simultaneous low-voltage differential signaling (LVDS) clocks, providing dedicated frame-first timing pulses to the system, while setting a minimum of parameters for the FPGA, a "plug and play" solution. The LMH1983 chip can save the fine-tuning time of the phase-locked loop, thus speeding up the time-to-market, which is superior to the solution using a discrete video/audio clock generator. The LMH1983 chip supports the SMPTE Serial Digital Interface (SDI) video standard and the AES3/EBU digital audio standard, which are standards commonly used in 1080p HD (HD) cameras and video capture, conversion, processing, editing and distribution equipment.
Taking the video processing and format converter plug-in as an example, the LMH1983 clock generator can simultaneously provide the required SMPTE 424M system clock (148.5MHz and 148.5/1.001MHz) for a new generation of FPGA chips. In general, the studio must "synchronize lock" the video equipment, while the LMH1983 chip provides a synchronized high-frequency clock for these devices, and the digital pixel rate of this clock is based on the horizontal and vertical timing signals in the reference video signal. Lock it up. Since some of the video needs to be embedded or removed from the audio signal, the LMH1983 chip provides synchronized audio and video clocks that lock to the video reference signal for such applications.
The LMH1983 chip features a two-stage phase-locked loop architecture with four phase-locked loops and three voltage-controlled oscillators, all integrated into a 40-pin LLP® package. The chip can utilize a variety of different compatible reference signals, such as the horizontal/vertical sync signal output from National Semiconductor's LMH1981 video sync separator, from SDI stream signals or a 27MHz clock source to produce synchronized SD (HD) video, HD Three clocks, video (twice) and audio. The LMH1983 chip has many other features, such as automatic input format detection, digital frequency preservation techniques that prevent loss of reference signals, easy setup of different audio/video output formats, and simultaneous lock or digital free-running modes.
The LMH1983 chip can distinguish HVF sync signals from major video standards and audio word clocks such as 27MHz, 10MHz and 32/44.1/48/96kHz. In addition, the chip also has an I2C compatible bus interface to set the chip's registers and read the chip's status parameters. The LMH1983 chip is powered by a 3.3V power supply and is extremely energy efficient. In addition, each built-in phase-locked loop can be independently turned on/off to save system power consumption.
The LMH1983 chip is available in volume quantities and is priced at $16 each in 1,000-unit quantities.
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