Xilinx FPGA user constraint file classification and syntax description

There are three types of constraint files in FPGA design: user design files (.UCF files), netlist constraint files (.NCF files), and physical constraint files (.PCF files), which can complete timing constraints, pin constraints, and region constraints. The relationship between the three types of constraint files is: the user writes the UCF file in the design input stage, then the UCF file and the design are combined to generate the NCF file, and finally the PCF file is generated after the implementation.
The UCF file is an ASC 2 code file that describes the constraints of the logic design and can be edited with a text editor and a Xilinx constraint file editor. The syntax of the NCF constraint file is the same as that of the UCF file. The difference between the two is: UCF file is input by the user, and the NCF file is automatically generated by the synthesis tool. When there is a conflict between the two, the UCF file is taken as the priority of the UCF. highest. The PCF file can be divided into two parts: one is the physical constraint generated by the mapping, and the other is the constraint input by the user. Similarly, the user-constrained input has the highest priority. In general, user constraints should be completed in the UCF file. It is not recommended to directly modify the NCF file and PCF file. The constraint file has a .ucf suffix, so it is also commonly referred to as a UCF file. There are two ways to create a constraint file, one is through the new method, and the other is done using the process manager. The first method: create a new source file, select "ImplementaTIon Constrains File" in the code type, and enter the name of the constraint file in "File Name". Click the "Next" button to enter the module selection dialog box, select the module to be constrained, then click "Next" to enter the next page, and then click the "Finish" button to complete the creation of the constraint file. The second method: In the project management area, set "Source for" to "Synthesis/ImplementaTIon". The “Constrains Editor” is a dedicated constraint file editor. You can open the “Constrains Editor” by double-clicking “Create TIming Constrains” under “User Constrains” in the process management area. It should be noted that the UCF file is size sensitive, the port name must be the same as the name in the source code, and the port name cannot be the same as the keyword. But the keyword NET is not case sensitive. The syntax of the UCF file: 1. The syntax of the grammar UCF file is: {NET|INST|PIN} "signal_name" Attribute; where "signal_name" refers to the name of the object being constrained, including the description of the level of the object; "Attribute" is the specific description of the constraint; Must end with a semicolon ";". You can add comments with "#" or "". It should be noted that UCF files are case sensitive, and the signal names must be the same as the case in the design, but the keywords of the constraints can be uppercase, lowercase, or even mixed case. For example: NET "CLK" LOC = P30; "CLK" is the constrained signal name, LOC = P30; is the specific meaning of the constraint, the CLK signal is assigned to the P30 pin of the FPGA. For all constraint files, using the same signal name as the constraint keyword or design environment reserved word will generate an error message unless it is enclosed in "", so when entering the constraint file, it is best to use " " to signal all signals Name the name.

2. Wildcards In UCF files, wildcards refer to "*" and "?". "*" can represent any string as well as empty, and "?" represents a character. When editing a constraint file, you can use a wildcard to quickly select a set of signals, all of which contain a partially shared string. For example: NET "*CLK?" FAST; all signals that contain the "CLK" character and end with one character, and increase its rate. In position constraints, you can use wildcard characters in line numbers and column numbers. For example: INST "/CLK_logic traverses level1 modules, but does not traverse lower-level modules
Pin and area constraint syntax (also available through Floorplanner constraints) LOC constraints are the most basic layout constraints and comprehensive constraints in FPGA design. They can define the position of the basic design unit in the FPGA chip, enabling absolute positioning, range positioning, and area positioning. . In addition, the LOC can constrain a set of basic units in a specific area. The LOC statement can either be written in the constraint file or added directly to the design file. In other words, the main functions of the FPGA underlying FPGA Editor, Floorplanner, and Pin and Region Constraint Editor in ISE can be done through LOC statements. LOC statement syntax INST "instance_name" LOC = locaTIon; where "location" can be any one or more legal locations in the FPGA chip. If there are multiple locations, they need to be separated by a comma "," as follows: LOC = location1, location2,...,locationx; Currently, it is not yet supported to put multiple logics in the same location and multiple logics as far as possible Multiple locations. It should be noted that the multi-position constraint does not locate the design at all locations, but in the place-and-route process, the layouter arbitrarily selects one of them as the final layout position.
The syntax for range positioning is: INST "instance_name" LOC=location:location [SOFT];
The commonly used LOC positioning statement [[wysiwyg_imageupload:169:]] uses LOC to complete the port definition. The syntax is as follows: NET "Top_Module_PORT" LOC = "Chip_Port"; where "Top_Module_PORT" is the signal port of the top-level module in the user design. "Chip_Port" is the pin name of the FPGA chip. There is a priority in the LOC statement. When the LOC port and its port are simultaneously connected, the priority of the connection constraint is the highest.
2. LOC attribute description
The LOC statement can constrain the pin location, CLB, Slice, TBUF, block RAM, hard multiplier, global clock, digital phase-locked loop (DLL), and DCM module by loading different attributes, which basically covers all the FPGA chips. Type of resource. It can be seen that the LOC statement is very powerful, and the following table shows the common attributes of LOC.

Timing constraint syntax (can also be constrained by the constraint editor)
Syntax of Timing Constraints in UCF Files Constraining UCF files, direct input from the Constrains Editor is the most convenient and straightforward way to add constraints. Here are a few common syntaxes:
1) Periodic constraints
The PERIOD constraint is a basic timing and synthesis constraint that is attached to the clock network. The timing analysis tool checks whether the timing of all synchronization elements in the clock domain meets the requirements based on the PERIOD constraint. It checks the delay of all paths connected to the synchronous timing constraint port. , but will not check the path of the PAD to the register.
The preferred method of the additional clock cycle constraint (Preferred Method) is as follows:
TIMESPEC "TS_identifier" = PERIOD "TNM_reference" period {HIGH|LOW} [high_or_low_time]
Among them, "[]" is optional, "{}" is mandatory, parameter period is the required clock period, you can use ps, ns, us or ms, etc., uppercase and lowercase, the default unit is ns. The HIGH|LOW keyword indicates whether the first pulse in the clock cycle is high or low, and high_or_low_time is the duration of the pulse. The default unit is also ns. If this is not provided, the default duty cycle is 50%.
TIMESPEC is a basic timing-related constraint identifier that indicates that this constraint is a timing specification. The TSidentifier consists of a letter TS and an identifier identifier (which is an ASCII string) that together form a timing specification.
For example, when defining a clock cycle constraint, first add a TNM_NET constraint on the clock network line clk, define all synchronization elements driven by the clk as a packet named sys_clk, and then define the clock cycle using the TIMESPEC constraint.
NET “clk” TNM_NET=”sys_clk”; #Define all synchronization elements of the clk driver as a group of sys_clk
TIMESPEC "TS_sys_clk" = PERIOD "sys_clk" 50 HIGH 30; # Define the referenceable timing specification TS_sys_clk,
#This specification specifies the clock condition of the sys_clk group. The syntax for defining a derived clock is as follows:
TIMESPEC "TSidentifier_2"=PERIOD "timegroup_name" "TSidentifier_1" [*or/] factor PHASE [+|-] phase_value [units]; # Define the second timing specification TSidentifier_2 whose content is the group named timegroup_name is the first
#a timing specification TSidentifier_1 derived where TSidentifier_2 is the derived clock to be defined, TSidentifier_1 is the defined clock, and factor indicates the relationship between the two periods, which is a floating point number. Phase_value indicates the phase relationship between the two, which is a floating point number. E.g:
Define the master clock clk0:
TIMESPEC "TS01" = PERIOD "clk0" 10.0 ns;
Define the derived clock clk180 whose phase is 180° out of phase with the main clock:
TIMESPEC "TS02" = PERIOD "clk180" TS01 PHASE + 5.0 ns;
Define the derived clock clk180_2, whose period is 1/2 of the main clock and delay 2.5ns:
TIMESPEC "TS03" = PERIOD "clk180_2" TS01 /2 PHASE + 2.5 ns;
2) Offset Constraint The offset constraint specifies the timing relationship between the external clock and the data input and output pins. It is only used for the (port) signal connected to the PAD and cannot be used for internal signals. Use this constraint to indicate to the integrated implementation tool the time at which the input data arrives, or the time at which the output data is stable, thereby adjusting the place and route process in the integrated implementation, enabling the input setup time of the FPGA/CPLD being developed and the input of the next stage of the circuit. The establishment time meets the requirements.
The basic syntax is as follows:
OFFSET = {IN|OUT} "offset_time" [units] {BEFORE|AFTER} "clk_name" [TIMEGRP "group_name"];
Where {IN|OUT} indicates whether the input or output is constrained, offset_time is the time difference between the data change of the FPGA pin and the valid clock edge, and BEFORE|AFTER indicates whether the time difference is before or after the valid clock edge, and TIMEGRP "group_name" is defined. The constrained trigger group, by default, constrains all triggers driven by this clock.
3) Grouping constraints Using the TNM (Timing Name) constraint, you can select the components that make up a group and assign a name to attach constraints to them. The TNM_NET (timing name for nets) constraint is only added to the network cable, and its role is basically the same as when the TNM is added to the network, that is, all valid synchronization components on the path where the network cable is located are part of the named group. The difference is that when the TNM constraint is added to the PAD NET, the value of TNM will be assigned to the PAD instead of the synchronization component on the path where the network cable is located, ie the TNM constraint cannot pass through the IBUF. This is not the case with TNM_NET constraints.
4) The general strategy for constraining additional constraints is to first attach the overall constraints, such as PERIOD, OFFSET, etc., and then attach special constraints to the local circuits. These special constraints are usually looser than the overall constraints, and the wiring can be improved by relaxing the constraints as much as possible. Pass rate, reduce the time of place and route.
The FROM_TO constraint defines timing constraints between two groups, controlling the logic and routing delay between the two. These two groups can be user-defined or defined. Users can define groups using TNM_NET, TNM, and TIMEGRP, while the definition group mainly includes FFS, LATCHES, PADS, and RAMS. The syntax is as follows:
TIMESPEC "TSname" = FROM "group1" TO "group2" value;
Where value is the delay time, which can be used to make a specific value or expression.
The MAXDELAY constraint defines the maximum delay on a particular network line. The syntax is as follows:
NET "net_name" MAXDELAY = value units;

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