The most obvious feeling compared to when we came here half a year ago is that although the Silicon Valley semiconductor industry has not yet regained its prosperity a few years ago, it has basically resumed its previous prosperity.
Every time I come to Silicon Valley for an interview, the author usually pays attention to the number of cars in the parking spaces of companies in the park as a barometer to judge the development status of the industry. Many parking lots were empty when they arrived here a few months ago, but they are now full of employees' cars, and the number and type of high-end cars have increased a lot. This provides evidence from one aspect of the above feelings. This article will introduce in detail the technical development of each company.
FPGA Hutch Consensus - Powerful Penetration of the ASIC Market Altera and Xilinx, currently struggling with 28nm FPGAs, share a common goal—contingently eroding the ASIC and ASSP territories, as well as having their own strategic priorities.
Altera emphasizes the agility of Altera President, CEO and Chairman of the Board John P. Daane first analyzed the macro market situation. The overall market size of the ASIC/ASSP and embedded sectors in 2011 was approximately US$114 billion, with an accessible market of approximately US$58 billion. Altera’s goal is to obtain a 1% share, or US$580 million. In addition, the PLD market is about 5 billion U.S. dollars, and Altera’s goal is 10%, or 500 million U.S. dollars. Daane pointed out that the company has changed a lot from 5 or 10 years ago and is no longer just an FPGA vendor. It is currently working more closely with system developers.
In general, when a system developer starts an ASIC or ASSP design, the functions in the software will be run on the CPU or hardware accelerated. Software has good flexibility and low development cost, but it has higher energy consumption when transferring data, storing or retrieving software instructions; hardware is not very flexible and development costs are high, but the advantage is low energy consumption. The programmable structure has certain flexibility, moderate development costs, and low energy consumption. Therefore, a good system architecture requires agile integration of software, hardware, and programmable structures. Daane said: "At present, only FPGAs are required for system development."
He illustrated the advantages of FPGAs with an example of a wireless base station vendor extending system capabilities in the mid-life of the device. The customer wanted to expand the 3G network and prepare for future field upgrades to LTE coverage. During the upgrade, the functions of the base station will be greatly changed, and the data rate handled will also be greatly improved.
In this project, Altera provides a variety of implementation options by selecting the appropriate process, high-speed transceiver, memory architecture, and external interface configuration to meet base station manufacturers' overall cost, power, and performance throughout the system equipment life cycle. The requirements, while protecting their IP interests.
Daane stressed: "Change implementation, not change IP. System developers can choose the correct implementation of each functional block in the system. Embedded HardCopy can provide designers with more flexibility in hardening dedicated IP blocks in the FPGA. For users For differentiated product design, our solutions include soft IP blocks, hard-core system IP, and HardCopy technology."
Arun Iyengar, vice president of military, industrial, computer, consumer, and storage divisions of Altera, highlighted the newly introduced 1080p/30fps Full HD video content analysis FPGA solution known as "the world's first." He cited the data from the partner and analysis technology vendor Eutecus that FPGA solutions can provide better flexibility and real-time analysis of high-definition video than DSP-based solutions.
Video content analysis is the intelligent analysis of video content through a computer to provide real-time information for related events. It is different from motion detection, which generates an alarm when motion is detected. It does not distinguish human or animal target attributes, trajectories, and whether they are entering prohibited areas. Different from graphic recognition technology, such as facial recognition. The video content analysis technology includes a variety of algorithms such as motion detection and determining whether it belongs to a possible threat according to user-defined rules.
Currently, the video analytics market faces the following challenges: installation costs for equipment, calibration, integration, and maintenance; the accuracy of the analysis results must reach more than 90%; the quality of the video source requires 1080p high-definition video; the processing engine of the camera requires low cost and low Power consumption; Real-time decision making requires 1-2 frames of low-latency target detection and alerting.
In this regard, 1080p Full HD video content analysis FPGA solutions can provide higher accuracy and fewer false alarms; full frame rate analysis at 30 frames per second, throughput up to 60 Mpixel per second; real-time detection and identification Comprehensive analysis at any time. In addition, custom functions such as image pipeline, compression, and motor control are also available.
Altera collaborated with Eutecus to develop a single-chip, multi-core video analytics engine MVE for the Cyclone IV FPGA and an MVE software graphical user interface (GUI). MVE1. The block diagram of version x is shown in the figure. The solution can be integrated into high-definition internet protocol (IP) cameras, so it can be used to detect vehicle turn conditions in various weather conditions, to predict possible vehicle collisions, to approach vehicle stops, and to perform red light behavior analysis.
According to Arun Iyengar, users do not need expensive NRE costs when analyzing FPGA designs using this 1080p Full HD video content; Altera will sell IP directly in royalty mode; for cost-sensitive users, they can purchase the required security devices. Enable IP.
For the Chinese market, Iyengar pointed out that many cities such as Chongqing and Shenzhen have the demand for millions of video surveillance cameras.
Xilinx Virtex-7 2000T FPGA Accelerates Alternate ASIC and ASSP
When interviewed by Xilinx headquarters, it coincided with the shipment of the world's largest capacity Virtex-7 2000T FPGA, so almost all topics were focused on this latest solution.
The Virtex-7 2000T has 6.8 billion transistors and 1954560 logic cells. "The capacity is equivalent to twice the market's largest 28nm FPGA." Xilinx's vice president, Liam Madden, did not forget to take advantage of rival Altera when introducing his product features.
We know that Altera released a 28-nm Stratix V FPGA with 3.9 billion transistors and 980,000 logic cells in mid-April 2011. It seems that the current application market of FPGAs is still not big enough to allow the hutchers' energy to be enough for each reason and to take care of others.
Madden emphasized that the performance of the Virtex-7 2000T determines its three major market goals:
First, accelerate the replacement of 20 million gate ASICs and ASSPs. In the current chip design, the NRE cost of a 28nm ASIC or ASSP has exceeded 50 million US dollars, and many chip manufacturers cannot afford such a high design cost. And this does not count on the ASIC to modify the design process, otherwise, the design cost will increase substantially by half. The Virtex-7 2000T's capacity is equivalent to 20 million gate-level ASICs, so it can replace the latter in large quantities. With a total investment cost almost the same, the two-year development time of the Virtex-7 2000T is 1/3 shorter than the ASIC required for three years. In addition, the power consumption is less than 30W, which is more than 1 times lower than the 70W power consumption of the ASIC.
Second, large-scale system integration. For situations where multiple FPGA design products are used today, the Virtex-7 2000T eliminates I/O interfaces between different ICs on the board and reduces overall system power consumption. In addition, partitioning, layout planning, and optimization can be efficiently performed to achieve optimal timing and performance.
Third, ASIC prototype and simulation design requirements. Since software development often takes a lot of time in the complex system development cycle, software development after the ASIC is completed will delay the development of the entire system. The Virtex-7 2000T prototype or simulation platform enables designers to immediately develop SoC software and accelerate the time-to-market process. In addition, IP vendors can use FPGAs to develop new IP blocks.
Every time I come to Silicon Valley for an interview, the author usually pays attention to the number of cars in the parking spaces of companies in the park as a barometer to judge the development status of the industry. Many parking lots were empty when they arrived here a few months ago, but they are now full of employees' cars, and the number and type of high-end cars have increased a lot. This provides evidence from one aspect of the above feelings. This article will introduce in detail the technical development of each company.
FPGA Hutch Consensus - Powerful Penetration of the ASIC Market Altera and Xilinx, currently struggling with 28nm FPGAs, share a common goal—contingently eroding the ASIC and ASSP territories, as well as having their own strategic priorities.
Altera emphasizes the agility of Altera President, CEO and Chairman of the Board John P. Daane first analyzed the macro market situation. The overall market size of the ASIC/ASSP and embedded sectors in 2011 was approximately US$114 billion, with an accessible market of approximately US$58 billion. Altera’s goal is to obtain a 1% share, or US$580 million. In addition, the PLD market is about 5 billion U.S. dollars, and Altera’s goal is 10%, or 500 million U.S. dollars. Daane pointed out that the company has changed a lot from 5 or 10 years ago and is no longer just an FPGA vendor. It is currently working more closely with system developers.
In general, when a system developer starts an ASIC or ASSP design, the functions in the software will be run on the CPU or hardware accelerated. Software has good flexibility and low development cost, but it has higher energy consumption when transferring data, storing or retrieving software instructions; hardware is not very flexible and development costs are high, but the advantage is low energy consumption. The programmable structure has certain flexibility, moderate development costs, and low energy consumption. Therefore, a good system architecture requires agile integration of software, hardware, and programmable structures. Daane said: "At present, only FPGAs are required for system development."
He illustrated the advantages of FPGAs with an example of a wireless base station vendor extending system capabilities in the mid-life of the device. The customer wanted to expand the 3G network and prepare for future field upgrades to LTE coverage. During the upgrade, the functions of the base station will be greatly changed, and the data rate handled will also be greatly improved.
In this project, Altera provides a variety of implementation options by selecting the appropriate process, high-speed transceiver, memory architecture, and external interface configuration to meet base station manufacturers' overall cost, power, and performance throughout the system equipment life cycle. The requirements, while protecting their IP interests.
Daane stressed: "Change implementation, not change IP. System developers can choose the correct implementation of each functional block in the system. Embedded HardCopy can provide designers with more flexibility in hardening dedicated IP blocks in the FPGA. For users For differentiated product design, our solutions include soft IP blocks, hard-core system IP, and HardCopy technology."
Arun Iyengar, vice president of military, industrial, computer, consumer, and storage divisions of Altera, highlighted the newly introduced 1080p/30fps Full HD video content analysis FPGA solution known as "the world's first." He cited the data from the partner and analysis technology vendor Eutecus that FPGA solutions can provide better flexibility and real-time analysis of high-definition video than DSP-based solutions.
Video content analysis is the intelligent analysis of video content through a computer to provide real-time information for related events. It is different from motion detection, which generates an alarm when motion is detected. It does not distinguish human or animal target attributes, trajectories, and whether they are entering prohibited areas. Different from graphic recognition technology, such as facial recognition. The video content analysis technology includes a variety of algorithms such as motion detection and determining whether it belongs to a possible threat according to user-defined rules.
Currently, the video analytics market faces the following challenges: installation costs for equipment, calibration, integration, and maintenance; the accuracy of the analysis results must reach more than 90%; the quality of the video source requires 1080p high-definition video; the processing engine of the camera requires low cost and low Power consumption; Real-time decision making requires 1-2 frames of low-latency target detection and alerting.
In this regard, 1080p Full HD video content analysis FPGA solutions can provide higher accuracy and fewer false alarms; full frame rate analysis at 30 frames per second, throughput up to 60 Mpixel per second; real-time detection and identification Comprehensive analysis at any time. In addition, custom functions such as image pipeline, compression, and motor control are also available.
Altera collaborated with Eutecus to develop a single-chip, multi-core video analytics engine MVE for the Cyclone IV FPGA and an MVE software graphical user interface (GUI). MVE1. The block diagram of version x is shown in the figure. The solution can be integrated into high-definition internet protocol (IP) cameras, so it can be used to detect vehicle turn conditions in various weather conditions, to predict possible vehicle collisions, to approach vehicle stops, and to perform red light behavior analysis.
According to Arun Iyengar, users do not need expensive NRE costs when analyzing FPGA designs using this 1080p Full HD video content; Altera will sell IP directly in royalty mode; for cost-sensitive users, they can purchase the required security devices. Enable IP.
For the Chinese market, Iyengar pointed out that many cities such as Chongqing and Shenzhen have the demand for millions of video surveillance cameras.
Xilinx Virtex-7 2000T FPGA Accelerates Alternate ASIC and ASSP
When interviewed by Xilinx headquarters, it coincided with the shipment of the world's largest capacity Virtex-7 2000T FPGA, so almost all topics were focused on this latest solution.
The Virtex-7 2000T has 6.8 billion transistors and 1954560 logic cells. "The capacity is equivalent to twice the market's largest 28nm FPGA." Xilinx's vice president, Liam Madden, did not forget to take advantage of rival Altera when introducing his product features.
We know that Altera released a 28-nm Stratix V FPGA with 3.9 billion transistors and 980,000 logic cells in mid-April 2011. It seems that the current application market of FPGAs is still not big enough to allow the hutchers' energy to be enough for each reason and to take care of others.
Madden emphasized that the performance of the Virtex-7 2000T determines its three major market goals:
First, accelerate the replacement of 20 million gate ASICs and ASSPs. In the current chip design, the NRE cost of a 28nm ASIC or ASSP has exceeded 50 million US dollars, and many chip manufacturers cannot afford such a high design cost. And this does not count on the ASIC to modify the design process, otherwise, the design cost will increase substantially by half. The Virtex-7 2000T's capacity is equivalent to 20 million gate-level ASICs, so it can replace the latter in large quantities. With a total investment cost almost the same, the two-year development time of the Virtex-7 2000T is 1/3 shorter than the ASIC required for three years. In addition, the power consumption is less than 30W, which is more than 1 times lower than the 70W power consumption of the ASIC.
Second, large-scale system integration. For situations where multiple FPGA design products are used today, the Virtex-7 2000T eliminates I/O interfaces between different ICs on the board and reduces overall system power consumption. In addition, partitioning, layout planning, and optimization can be efficiently performed to achieve optimal timing and performance.
Third, ASIC prototype and simulation design requirements. Since software development often takes a lot of time in the complex system development cycle, software development after the ASIC is completed will delay the development of the entire system. The Virtex-7 2000T prototype or simulation platform enables designers to immediately develop SoC software and accelerate the time-to-market process. In addition, IP vendors can use FPGAs to develop new IP blocks.
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