UltraSoC, a pioneering company in embedded analytics technology, is thrilled to announce the full-scale availability of its comprehensive suite of debug and monitoring intellectual property (IP) products tailored specifically for ARM's recently launched AMBA 5 Coherent Hub Interface (CHI) Issue B specification. The CHI Issue B specification represents ARM's most sophisticated bus protocol yet, designed to support the intricate demands of modern system-on-chip (SoC) designs. UltraSoC’s offerings stand as the sole products in the market that cater exclusively to the unique requirements of engineers working with the CHI Issue B specification.
As a semiconductor IP product, UltraSoC’s monitoring and debugging solutions provide robust testing capabilities, aiding in problem-solving for next-generation coherent cache SoC designs based on the CHI Issue B specification. These solutions enable customers to fully leverage the benefits of the CHI Issue B specification, including enhanced security, data throughput, and reduced latency. Addressing consistency issues has become increasingly vital for designers of complex systems, and UltraSoC was honored to be selected as the keynote speaker on this topic at the ARM TechCon conference this year. Taking place October 24-26, 2017, in Santa Clara, the conference will focus on advancing the understanding of these critical design challenges.
By supporting CHI Issue B, UltraSoC continues its mission of delivering feature-rich, system-level monitoring and debugging solutions that surpass vendor-specific systems like ARM’s CoreSight. Designers can utilize UltraSoC products either as a "full coverage" option to access functionalities beyond what their traditional debug systems offer or as a complete replacement. This integrated approach to debugging is particularly advantageous in multicore designs since UltraSoC supports all common CPU architectures and even open-source processor platforms such as RISC-V.
"Gadge Panesar, UltraSoC’s Chief Technology Officer, highlighted the importance of CHI, stating, "CHI is a crucial protocol that delivers key performance metrics for on-chip networks in SoCs; however, it poses significant design challenges, especially with the advent of the updated Issue B version. While basic performance statistics are useful, they are insufficient on their own. This calls for a specialized team like UltraSoC, which focuses on monitoring and debugging, along with a comprehensive solution to back it up. This is the vast ARM ecosystem’s energy, allowing customers to tap into the expertise of third-party solution providers like UltraSoC to swiftly and efficiently resolve complex design issues."
Modern SoCs, especially those deployed in data centers, enterprise IT systems, or automotive applications, heavily depend on flawless and efficient internal interconnect technologies with an on-chip network aggregation center. The development philosophy behind the AMBA 5 CHI specification aims to ensure that this internal interconnect doesn't turn into a bottleneck due to increasing traffic and system complexity. Designers can tailor the implementation of CHI according to power, performance, and chip area requirements. Yet, within these SoC designs and system configurations, several potential issues may arise, impacting overall system performance, such as traffic issues related to cache coherency. By employing UltraSoC’s monitoring IP for CHI Issue B, designers of these intricate SoCs can simultaneously assess performance and diagnose or predict such issues.
The CHI Issue B specification incorporates several significant updates that directly contribute to improving latency and throughput. Two of the most notable enhancements are far-atomic operations and cache hiding. Far-atomic operations allow for high-frequency updates of shared data across internal interconnects, while cache hiding enables accelerators or I/O devices to store critical data in a CPU cache, ensuring low-latency channels. For more details on the new AMBA 5 CHI Issue B specification, including atomic operations, cache hiding, and other performance improvements such as direct data transfer, readers are encouraged to explore the ARM blog.
Last year, UltraSoC introduced the industry’s first monitoring and debugging IP product for the earlier (Aussie A) AMBA 5 CHI NoC specification, expanding its protocol-aware monitor product line for on-chip internal interconnects. Since then, UltraSoC has collaborated closely with numerous leading customers to develop a CHI Issue B solution capable of validating protocol implementations, accelerating overall chip design integration, and minimizing NoC overhead. This commitment to innovation underscores UltraSoC’s leadership in providing cutting-edge solutions for the semiconductor industry.
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