Over the past few years, many system designers have been incorporating DDR4 RAM components into their designs. As product performance continues to rise and power budgets shrink, the demand for faster memory devices remains constant. In 2013, even though DDR4 was already widely used in mainstream systems, the DDR5 standard was still in its specification phase. Although the official DDR5 specification had not yet been released, the key features were already well understood: DDR5 promises double the bandwidth of DDR4 and more efficient power management.
As the market awaits the official adoption of DDR5, it’s likely that by late 2018, system designers would feel increasing pressure to understand the implications of this new standard. They want to know how much it will cost to upgrade their systems to support DDR5’s enhanced performance, higher data rates, and different power requirements. Therefore, they hope to begin prototype design as early as possible, based on known DDR5 characteristics, and then explore how to integrate the DDR5 bus into their products.
For experienced engineers, building a prototype with a new memory interface starts with obtaining a device model that accurately represents the interface behavior. This model is then used to validate and simulate new features using simulation tools or environments based on the DDR5 specification. Unfortunately, most designers face a roadblock here—there are no available DDR5 RAM models yet.
Some might argue that a memory device is simply a receiver during write cycles and can be represented by existing IBIS receiver models. But this was true 15 years ago. Today, things are far more complex. Engineers working with high-speed DDR4 (like 3200 Mbps) know why. Modern high-speed memories use techniques like equalization and serial link filtering to maintain signal integrity. These features are only modeled through IBIS-AMI models, which are provided by manufacturers. With DDR5 expected to run at even higher speeds and with lower voltage swings, equalization becomes even more critical. Thus, system designers need advanced controller and memory models to accurately simulate the DDR5 interface. However, these models are not yet available from manufacturers.
This leaves designers in a tough spot: they’re eager to start building systems that take advantage of DDR5’s capabilities, but lack the necessary models for testing. What’s worse, these models may not be available for some time. The biggest fear among design engineers is that competitors could gain an early advantage by accessing these models first and launching products ahead of them. Even if models do become available, there’s another concern—will current simulation tools support the new data transfer features required for DDR5?
As a tool provider, one of our main goals is to help engineers break free from model dependencies and give them the flexibility to create their own models for emerging interfaces and technologies. Can this be done? For Sigrity users, the answer is yes. In fact, for engineers using Sigrity SystemSI 2017, the solution is already in their hands! It may come as a surprise, but it's a reality.
Sigrity SystemSI includes an embedded IBIS-AMI model generator called AMIBuilder. This tool uses the SystemSI GUI to accept user-defined AMI model parameters and generate AMI models with either user-specified or default IBIS/O buffer models. Our users, including the Cadence IP team, have been using this tool to create DDR4 models. Recently, some have used FFE/DFE technology to generate DDR5 AMI models and successfully completed test system designs, predicting DDR5 behavior with accuracy.
Of course, this raises another concern: even with a DDR5 AMI model, will my simulation tools support the necessary functions for DDR5 bus simulation? SystemSI comes equipped with a power-saving solution that leverages Cadence’s patented channel emulation technology for accurate bus characterization and simulation.
So, for anxious design and SI engineers, there’s no need to wait for the final DDR5 specification or for manufacturers to release models. Sigrity SystemSI can help you create prototypes and understand how DDR5 will perform in your application. Don’t worry—your path forward is clear.
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