FPGA core knowledge (3): those simulations that make FPGA beginners entangled

The core tips of the electronic enthusiast network : For FPGA beginners, how to correctly understand and understand the simulation of FPGA is the key. According to the requirements of the majority of FPGA beginners and enthusiasts, the editors of the electronic enthusiast network are based on the introduction of many seniors who have many years of experience in the field of FPGA. Hereby, we will organize and share the following brief introductions on various FPGA simulations. If you have any questions that need to be added or have any inadequacies in this article, please let us know in the comments. At the same time, you can also join the electronic enthusiast network FPGA technology exchange group (QQ) to discuss with everyone, and welcome everyone to join the electronic enthusiast network forum to participate in the interaction.

FPGA core knowledge (3): those simulations that make FPGA beginners entangled

Beginners learning FPGAs will surely be confused by its various simulations. For example, pre-simulation, post-simulation, functional simulation, timing simulation, behavioral level simulation, RTL-level simulation, post-synthesis simulation, gate-level simulation, post-layout simulation.

Simulation form of Quartus and Modelsim software

The Quartus II has two forms of simulation: 1. Functional simulation; 2. Timing simulation.

The two simulation forms of Quartus II calling Modelsim are: 1. RTL level simulation; 2. Gate-level simulation.

The following contents have been verified by data, as follows:

Understanding Method One

When simulating with quartus, it is divided into functional simulation (al) and timing simulation (TIming);

When using Modelsim-Altera, it is divided into functional simulation (RTL), post-synthesis and gate-level simulation (Gate-level). Among them, functional simulation is also called pre-simulation, and layout and routing simulation is also called post-simulation.

Note: The functional simulation (RTL) here is not the same as the functional simulation (al) in 1, the former is the HDL level simulation, and the latter is the functional simulation of the gate level netlist.

(1) When calling Modelsim-Altera for RTL simulation in quartus (provided that Modelsim-Altera is selected in a third-party simulation tool), the steps are as follows:

a) write source files and test files;

b) Assignment-"setTIng-"simulaTIon-" does not select run gate leve simulaTIon. .. , select nativelink-"Add test file, fill in the file name;

c) start analysis&elabration;

d) Tools-"start RTL simulation;

(2) After the synthesis, the simulation is generally not done.

(3) When calling Modelsim-Altera for Gate-level simulation in quartus (provided that Modelsim-Altera is selected in the third-party simulation tool), the steps are as follows:

a) write source files and test files;

b) Assignment-"setting-"simulation-" select run gate leve simulation. .. , select nativelink-"Add test file, fill in the file name;

c) full compilation;

Evaluation : For Assignment-"setting-"simulation-""run gate leve simulation automatically after comlilation", there is no need to explain it at all. It is completely unnecessary to select it. You need to add the test file testbench at the setting point (if you don't add it) When quartus calls out the modelsim software, you need to manually add the compiler, which is added below. If you want RTL level simulation, then you only need to analyze and synthesize quartus ii, then click Tools->Run EDA Simulation tool->Run RTL Simulation, the software will automatically compile the source files and test files in modelsim software. , the waveform is simulated. If you want a Gate-level simulation, then you need to fully compile the project for quartus ii, then click Tools->Run EDA Simulation tool->Run Gate-level Simulation, the software will automatically netlist file.vo(verilog The output file) or .vho (VHDL output file) and test files are compiled in modelsim software, and the standard delay file SDF (.sdo) is added to modelsim to simulate the waveform.

Added : By the way, if the test file testbench is not set in Assignment-"setting-"simulation, whether it is in RTL or Gate-level simulation, Quartus only sends .vo or .vho files after calling modelsim. The modelsim is compiled, and then the testbench needs to be compiled manually, and the .sdo file needs to be added manually during the Run Gate-level Simulation simulation, which is relatively cumbersome.

Understanding Method 2

Modelsim-Altera simulations are generally divided into functional simulation, pre-simulation (integrated post-simulation) and post-simulation (timing simulation or post-layout simulation).

According to the design needs, after writing the code (Verilog hdl, Vhdl, system Verilog), first perform the function simulation to verify whether the written code can complete the design function; the pre-simulation is also called the post-synthesis simulation, that is, after the Quartus II completes the synthesis, verify The function of the design; the post-simulation is also called the timing simulation or the post-layout simulation, which is the simulation after adding the delay. For small-scale designs with short compilation times, only functional simulation and post-simulation are generally performed.

Understanding Method 3

Modelsim is a software that is specifically designed to perform simulations and post-simulations. Pre-simulation is also called functional simulation. The main purpose is to verify whether the function of the circuit meets the design requirements. It is characterized by not considering the circuit gate delay and line delay, mainly to verify whether the circuit is consistent with the ideal situation. The synthesizable FPGA code is described in the RTL-level code language, and its input is RTL-level code and testbench. Post-simulation is also called timing simulation or post-layout simulation. It refers to the influence of path delay and gate delay of the circuit after the circuit has been mapped to a specific process environment. Can the verification circuit meet the design concept under certain timing conditions? Process, whether there is a timing violation. The input file is a gate-level netlist abstracted from the placement and routing results, a testbench, and a standard delay file that is extended to sdo or sdf. The standard delay file of sdo and sdf not only includes the gate delay, but also includes the actual wiring delay, which can better reflect the actual working condition of the chip. Generally, post-simulation is a must, check whether the design timing is consistent with the actual FPGA operation, and ensure the reliability and stability of the design.

Understanding Method 4

The difference between pre-simulation and post-simulation: pre-simulation refers to the pre-synthesis simulation, that is, behavior-level simulation, such as the simulation of writing code directly in Modelsim. Post-simulation refers to the integrated simulation, which is functional simulation. For example, if you write a counter in Modelsim with VHDL, the behavior level is simulated. You add it to quartus or other comprehensive tools for synthesis. After synthesis, the function netlist is generated. It converts the behavior language into a register. Level language, this time you add it to Modelsim to simulate the post-simulation. After the simulation is successful, you have to map, place and route in quartus, perform timing analysis after completion, generate timing netlist, describe the device gate or The delay of the wiring, and finally add the delay netlist and the function netlist together to the Modelsim simulation called gate level simulation.

The difference between gate level simulation and timing simulation: gate level simulation is the netlist file .vo generated by quartus. The gate level does not consider the interconnect delay, and the second considers the delay of the device. Timing simulation is a simulation that includes timing relationships after selecting specific devices and routing. It mainly verifies whether time constraints, delays, maximum operating frequencies, and consumed resources are met. Timing simulation is the need to add a delay file .sdo.

Understanding Method Five

In a broad sense, simulation verification includes functional and timing simulation and circuit verification. Simulation refers to the complete testing of the implemented design using the design software package to simulate the actual working conditions in the physical environment. Divided from the level of simulation, mainly divided into:

Pre-simulation, also known as functional simulation or behavioral level simulation. It means that only the logic function is tested and simulated to understand whether the function it implements meets the requirements of the original design. The simulation process does not include timing information, and does not involve hardware characteristics of specific devices, such as delay characteristics.

Post-simulation, also known as post-layout simulation or timing simulation. It refers to the extraction of the relevant device delay, wiring delay and other timing parameters, and based on this simulation, it is very close to the real device operation simulation. There are some other simulation processes for different tools and vendors, but they fall into these two categories.

There are three phases that can be simulated for the FPGA design process:

The first stage is the register transfer level (RTL) simulation, which verifies the syntax and basic functions of the design (without timing information);

The second stage is the simulation of specific FPGA manufacturer technology. This level of simulation is a functional level simulation performed after synthesis and before implementation. The functional level simulation generally verifies whether the correct function required by the designer can be obtained after synthesis.

The third stage is gate level simulation. This level of simulation is to simulate the gate level timing after implementation. The gate level simulation shows the actual delay due to layout and routing.

Understanding Method 6

Pre-imitation: Functional and performance simulation and verification for RTL code.

Post-imitation: 1. Pre-layout, this is a post-synthesis simulation, mainly whether the logic function after the imitation is correct, and the comprehensive timing constraints are correct.

2. post-layout, this is the post-layout simulation, because the line delay information is added, so the simulation of this step is the closest to the behavior of the real chip, and it is also used to simulate whether the chip timing constraint is added correctly, whether it is still after the layout and wiring. Meet the timing.

Understanding Method 7

Functional simulation simulates the function of the design input, considering an idealized situation with no gate delay and no routing delay.

The integrated process compiles the design input into a logical connection consisting of basic logic units such as AND, OR, NOT, RAM, and flip-flops, that is, a netlist, and outputs a netlist file in a standard format such as edf or edn. After the synthesis, the integrated generated standard delay file is back-labeled into the comprehensive simulation model to estimate the impact of the gate delay on the circuit.

Implementation and routing, according to the model of the selected chip, the integrated output logic netlist is adapted to the specific FPGA/CPLD. The most important process in the implementation process is Place and Route: the layout adapts the logic unit to the inherent hardware structure inside the FPGA; the wiring uses various interconnection resources inside the FPGA according to the topology of the layout. Connect the components reasonably and correctly. Timing simulation reverses the layout information of the layout and routing to the design netlist for simulation. At this time, the simulation delay file information is the most complete, including the gate delay and the wiring delay, so the simulation after wiring is the most accurate, which can better reflect the actual working condition of the chip.

The following is a personal glimpse : From the above analysis, we can give some equals to some of the nine simulation nouns mentioned in the article.

Pre-simulation = functional simulation = behavioral level simulation = RTL level simulation

Then the simulation can be divided into two steps. The first step is pre-distribution simulation, that is, the post-synthesis simulation is mainly to verify whether the logic function is correct, and the integrated timing is correct. The second step is post-layout simulation, that is, post-simulation. = Timing Simulation = Post-layout Simulation = Gate-level simulation. This level of simulation is closest to the chip, and the line delay is added to it.

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